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for technical support and more information, see inside back cover or visit www.ti.com features ? input voltage: 36 v to 75 v ? designed for ac6 adsl line-interface driver/receivers ? powers up to 32 channels ? quad outputs (8 v, 3.75 v) ? dual logic on/off control ? output current limit ? unbalanced load protection ? fixed frequency operation ? over-temperature shutdown ordering information PT4701 ? ? ? ? ? = 8.0/3.75 v pt series suffix (pt1234 x ) case/pin order package configuration suffix code vertical n (enm) horizontal a (enn) smd c (enp) (reference the applicable package code drawing for the dimensions and pc layout) typical application PT4701?48v description the pt 4701 excalibur? power module is a 35-watt quad-output dc/dc converter that is designed to meet the power requirements of texas instruments tnetd7112. the tnetd7112 is a dual-channel line-interface driver/receiver that compliments the ac6 adsl chipset for use in pots (plain old telephone service) applications. to conserve power, the tnetd7112 line drivers require two pairs of complimentary power supply voltages. these are 8 v and 3.75 v respectively. the PT4701 module operates from a standard (C48 v) telecom central office supply and provides all four supply voltages as two com- plimentary balanced loads. (this product is not suitable for unbalanced load applications.) the load capacity allows the PT4701 to operate up to 16 line-driver ics, representing 32 adsl channels. the PT4701 incorporates many features to simplify system integra- tion. these include a flexible on/off enable control, input under-voltage lock-out, and over-temperature pro- tection. all outputs are short-circuit protected, and internally sequenced to meet the tnetd7112 power-up and power-down requirements. the module is packaged in a space-saving solderable copper case, requires no heat sink, and can occupy as little as 1.2 in 2 of pcb area. co 1 , co 2 = required 33 f co 3 , co 4 = required 150 f en1 & en2 pins: see on/off enable logic 35-w quad-output dc/dc converter for dsl ? under-voltage lockout ? 1500 vdc isolation ? space-saving solderable case 1.2 sq. in. pcb area (suffix n) ? surface mountable ? ipc lead free 2 ? safety approvals: (pending) ul60950 csa 22.2 950 ? dual-channel adsl driver/receiver (tnetd7112) txp rxp rxn txn veehs vcchs veel vccl PT4701 +v in ?v in en1 en2 vo 2 adj vo 1 adj +vo 1 ?vo 1 +vo 2 ?vo 2 com +v in ?v in +3.75 v ?3.75 v +8 v ?8 v veeh vcch power filter power filter to additional channels co 1 33 f + co 2 33 f + co 3 150 f + co 4 150 f + com 1 3 4 2 20 19 18 21 16 15 14 17 agnd dgnd slts182a - february 2003 - revised april 2003
for technical support and more information, see inside back cover or visit www.ti.com pin function 1+vin 2Cvin 3 en 2 4 en 1 5 do not connect 6 do not connect 7 do not connect PT4701 ? 48v 35-w quad-output dc/dc converter for dsl on/off enable logic pin descriptions pin 3 pin 4 output status 1 off 10 on 0 off notes: logic 1 =open collector logic 0 = Cvin (pin 2) potential for positive enable function, connect pin 4 to pin 2 and use pin 3. for negative enable function, leave pin 3 open and use pin 4. +vin: the positive input supply for the module with respect to Cv in . when powering the module from a C48v telecom central office supply, this input is connected to the primary system ground. ?vin: the negative input supply for the module, and the 0vdc reference for the en 1, and en 2 inputs. when powering the module from a +48-v supply, this input is connected to the 48-v(return). en 1: the negative logic input that activates the module output. this pin must be connected to Cv in to enable the modules outputs. a high impedance disables the modules outputs. en 2: the positive logic input that activates the module output. if not used, this pin should be left open circuit. connecting this input to Cv in disables the modules outputs. +vo 1: this is the positive high-output voltage. it is the balanced compliment of (Cvo 1 ) and referenced to the secondary com node. ?vo 1: the negative high-output voltage, which is the balanced compliment of (+vo 1 ) with respect to com. +vo 2: this is the positive low-output voltage. it is the balanced complement of (Cvo 2 ) and referenced to the secondary com node. ?vo 2: the negative low-output voltage, which is the balanced compliment of (+vo 2 ) with respect to com. com: this is the common node and the secondary reference for all four regulated output voltages. it provides a return for any unbalanced load current, and is dc isolated from the input supply pins. vo 1 adjust: using a single resistor, this pin allows the simultaneous adjustment of both +vo 1 and -vo 1 magnitude with respect to the com node. adjust- ment can be higher or lower than the preset value. if not used this pin should be left open circuit. vo 2 adjust: using a single resistor, this pin allows the simultaneous adjustment of both +vo 2 and -vo 2 magnitudes with respect to the com node. adjust- ment can be higher or lower than the preset value. if not used this pin should be left open circuit. environmental specifications characteristics symbols conditions min typ max units operating temperature range t a over v in range C40 85 (i) c solder reflow temperature t reflow surface temperature of module pins or case 215 (ii) c storage temperature t s C40 125 c mechanical shock per mil-std-883d, method 2002.3 500 gs 1 msec, ? sine, mounted mechanical vibration mil-std-883d, method 2007.2 suffix a 15 (iii) gs 20-2000 hz suffix n, c 20 (iii) weight vertical/horizontal 50 grams shutdowntemperature otp 115 125 c flammability meets ul 94v-o notes: (i) see soa curves or consult factory for appropriate derating. (ii) during solder reflow of smd package version, do not elevate the module case, pins, or internal component temperatures above a peak of 215 c. for further guidance refer to the application note, reflow soldering requirements for plug-in power surface mount products, (slta 051). (iii) only the case pins on through-hole pin configurations (n & a) must be soldered. for more information see the applicable pa ckage outline drawing. pin function 8 pin not present 9 pin not present 10 pin not present 11 pin not present 12 pin not present 13 pin not present 14 +vo 1 pin configuration note: shaded functions indicates those pins that are at primary-side potential. all other pins are referenced to the secondary. pin function 15 com 16 Cvo 1 17 vo 1 adjust 18 +vo 2 19 com 20 Cvo 2 21 vo 2 adjust slts182a - february 2003 - revised april 2003
for technical support and more information, see inside back cover or visit www.ti.com PT4701 ? 48v 35-w quad-output dc/dc converter for dsl PT4701 electrical specifications (unless otherwise stated, the operating conditions are:- t a =25 c, v in =48 v, and i o =i o max) PT4701 characteristics symbols conditions min typ max units output current io 1 , io 2 balanced load vo 1 (8.0 v) 0 1.25 (1) a vo 2 (3.75 v) 0 1.75 (1) load imbalance vo 1 100 (2) ma vo 2 100 (2) transient imbalance (<1 ms) vo 1 150 ma vo 2 150 input voltage range v in continuous 36 75 v surge (1 minute) 80 set-point voltage vo 1 , vo 2 either output to com vo 1 7.76 8.0 8.24 v vo 2 3.82 3.94 4.06 (3) temperature variation reg temp C40 c t a +85 c, i o =i o min vo 1 0.5 %v o vo 2 0.5 line regulation reg line all outputs, over v in range 0.05 0.25 %v o load regulation reg load all outputs, 0 i o i o max 0.2 0.5 %v o total output voltage variation ? v o tot includes set-point, line, load, vo 1 (8.0 v) 7.6 8.4 v C40 c t a +85 c vo 2 (3.75 v) 3.75 4.13 (3) efficiency 85% v o ripple (pk-pk) v n measured from each output to com, vo 1 10 mv pp 0 to 20 mhz bandwidth vo 2 5 transient response t tr 0.1 a/s load step, 50 % to 75 % i o max 100 sec v os v o over/undershoot 2 %v o output adjust range vo x adj each v o adjusted as pair 10 %v o balanced load io lim shutdown, auto restart vo 1 1.5 (1) a current limit threshold vo 2 2.5 (1) unbalanced load i o com sc shutdown & latch off 200 (2) ma shutdown threshold (within 1 ms) switching frequency ? s over v in and i o ranges 550 600 650 khz under voltage lockout v on v in increasing 34 v v off v in decreasing 32 enable control (pins 3 & 4) referenced to Cv in (pin 2) high-level input voltage v ih 4 open (4) v low-level input voltage v il C0.2 0.8 (4) low-level input current i il pin connected to Cv in (pin 2) C0.16 C0.27 ma standby input current i in standby pins 3 & 4 open circuit 5 20 ma internal input capacitance c int 1 f external output capacitance c o each output to com vo 1 33 1,000 (5) f vo 2 150 1,000 (5) primary/secondary isolation v iso 1500 v c iso 2,200 pf r iso 10m ? notes: (1) a balanced load is defined as the current flowing out of (+vo x ) being to equal that flowing into (Cvo x ). the current flowing in the com termnal is zero. (2) the load imbalance is the difference between the current flowing out of (+vo x ) and flowing into (Cvo x ). the difference flows in the com terminal. (3) the nominal output voltage of vo 2 is 3.94 v. the output voltage and tolerance is defined as 3.75 v, C0%, +10%. (4) the enable inputs (pins 3 & 4) have internal pull-ups. leaving pin 3 open-circuit and connecting pin 4 to Cv in allows the the converter to operate when input power is applied. the maximum open-circuit voltage is 5v. (5) capacitance added to each pair of complimentary output voltages (vo x ) must be divided equally between (+vo x ) and (Cvo x ) with respect to the com termnial. e.g. co 1 must equal co 2 , and co 3 must equal co 4 . slts182a - february 2003 - revised april 2003
for technical support and more information, see inside back cover or visit www.ti.com PT4701 ? 48v output ripple vout 1 vs iout 1 & iout 2 performance characteristics; v in =48 v (see note a) typical characteristics note a: all characteristic data in the above graphs has been developed from actual products tested at 25c. this data is considered typ ical data for the isr. 35-w quad-output dc/dc converter for dsl output ripple vout 2 vs iout 1 & iout 2 load regulation vout 1 vs iout 1 load regulation vout 2 vs iout 2 cross regulation vout 1 vs iout 2 cross regulation vout 2 vs iout 1 0 5 10 15 20 25 0 0.25 0.5 0.75 1 1.25 iout 1 ( a ) vo 1 ripple (mv) 1.75 1.5 1.25 1 0.75 0.5 0.25 iout 2 0 5 10 15 20 25 0 0.25 0.5 0.75 1 1.25 1.5 1.75 iout 2 ( a ) vo 2 ripple (mv) 1.25 1 0.75 0.5 0.25 iout 1 7.96 7.97 7.98 7.99 8 8.01 8.02 8.03 8.04 0 0.25 0.5 0.75 1 1.25 iout 1 ( a ) load regulation | ? vout 1 | (v) vo ( + ) vo ( ? ) 3.92 3.925 3.93 3.935 3.94 3.945 3.95 3.955 3.96 0 0.25 0.5 0.75 1 1.25 1.5 1.75 iout 2 ( a ) load regulation | ? vout 2 | (v) vo ( + ) vo ( ? ) 7.96 7.97 7.98 7.99 8 8.01 8.02 8.03 8.04 0 0.25 0.5 0.75 1 1.25 1.5 1.75 iout 2 ( a ) cross regulation | ? vout 1 | (v) vo ( + ) vo ( ? ) 3.92 3.925 3.93 3.935 3.94 3.945 3.95 3.955 3.96 0 0.25 0.5 0.75 1 1.25 iout 1 ( a ) cross regulation | ? vout 2 | (v) vo ( + ) vo ( ? ) slts182a - february 2003 - revised april 2003
for technical support and more information, see inside back cover or visit www.ti.com PT4701 ? 48v performance characteristics; v in =48 v (see note a) typical characteristics note a: all characteristic data in the above graphs has been developed from actual products tested at 25c. this data is considered typ ical data for the isr. note b: soa curves represent operating conditions at which the internal components are at or below the manufacturers maximum rated ope rating temperatures. PT4701 safe operating area (soa) (see note b) (all outputs proportionally loaded from 0 to 100 % of full load) 35-w quad-output dc/dc converter for dsl efficiency vs iout 1 & iout 2 power dissipation vs iout 1 & iout 2 soa vs total output power; v in =48 v 40 50 60 70 80 90 0 0.25 0.5 0.75 1 1.25 iout 1 ( a ) efficiency - % 1.75 1.5 1.25 1 0.5 iout 2 0 1.5 3 4.5 6 7.5 9 0 0.25 0.5 0.75 1 1.25 iout 1 ( a ) pd - watts 1.75 1.5 1.25 1 0.75 0.5 0.25 0.1 iout 2 20 30 40 50 60 70 80 90 0 5 10 15 20 25 30 35 out p ut power ( w ) ambient temperature ( c) 300lfm 200lfm 150lfm 100lfm nat conv airflow slts182a - february 2003 - revised april 2003
for technical support and more information, see inside back cover or visit www.ti.com PT4701 operating features of the PT4701 quad-output dc/dc converter for dsl line drivers balanced load fault protection a balanced load fault is the result of excess current flowing from one +v o output directly to the corresponding Cv o output. the current flowing in or out of the com node (pins 15 & 19) under this condition is within normal operating limits. both ()dual outputs from the PT4701 dc/dc converter incorporate protection against this type of load fault. this includes an absolute current limit in combination with a fault timeout period. when the balanced fault current from either dual output exceeds the balanced load current limit threshold (see data sheet specifications), the converter initially limits the fault current to approximately 150 % of the maximum output current rating. if the fault persists for more than 20 ms the converter shuts down, forcing the voltage at all four regulated outputs to simultaneously fall to zero. following shutdown the converter will periodically attempt to recover by executing a soft-start power-up. the converter will continually cycle through successive over-current shutdowns and restarts until the fault is removed. imbalanced load fault protection an imbalanced load fault is the result of excess current flowing between any one of the +v o (or the Cv o ) outputs, and the com node (pins 15 & 19). when the current sensed in the com node exceeds the unbalanced load shutdown threshold (see data sheet specifications), the PT4701 shuts down and latches off within 1ms. once latched off, the module must be reset by momentarily interrupting the input power source. over-temperature protection the PT4701 dc/dc converter has an internal tem- perature sensor, which monitors the temperature of the modules internal components. if the sensed temperature exceeds a nominal 115 c, the converter will shut down. the converter will automatically restart when the sensed temperature returns to about 100 c. under-voltage lock-out the under-voltage lock-out (uvlo) circuit prevents operation of the converter whenever the input voltage to the module is insufficient to maintain output regulation. the uvlo has approximately 2 v of hysterisis. this is to prevent oscillation with a slowly changing input volt- age. below the uvlo threshold the module is off and the enable control inputs, en1 and en2 are inoperative. primary-secondary isolation the PT4701 dc/dc converter incorporates electrical isolation between the input terminals (primary) and the output terminals (secondary). all converters are production tested to a withstand voltage of 1500 vdc. the isolation complies with ul60950 and en60950, and the require- ments for operati onal isolation. this allows the converter to be configured for either a positive or negative input voltage source. the regulation control circuitry for these modules is located on the secondary (output) side of the isolation barrier. control signals are passed between the primary and secondary sides of the converter. the data sheet pin descriptions and pin-out information provides guid- ance as to which reference (primary or secondary) that must be used for each of the external control signals. input current limiting the converter is not internally fused. for safety and overall system protection, the maximum input current to the converter must be limited. active or passive current limiting can be used. passive current limiting can be a fast acting fuse. a 125-v fuse, rated no more than 5 a, is recommended. active current limiting can be imple- mented with a current limited hot-swap controller. application notes
application notes for technical support and more information, see inside back cover or visit www.ti.com adjusting the output voltages of the pt 4701 quad- output dc/dc converters the PT4701 quad-output dc/dc converter produces two pairs of balanced v o complimentary output voltages. the magnitude of each balanced pair of outputs may be adjusted higher or lower by up to 10 %. the adjustment method uses a single external resistor 1 , which adjusts the magnitude of the respective +v o and Cv o simultaneously. the value of the resistor determines the m agnitude of adjustment, and the placement of the resistor determines the direction of adjustment (increase or decrease). the resistor values can be calculated using the appropriate formula (see below). the formula constants are provided in table 3-2. alternatively the resistor value may be selected directly from table 3-3 and table 3-4, for vo 1 and vo 2 respectively. the placement of each resistor is as follows. adjust up: to increase the magnitude of the complimentary output voltages, add a resistor r 1 between the appropriate vo x adj (vo 1 adj or vo 2 adj) and the -vo x voltage rail. see figure 3-1(a) and table 3-1 for the resistor placement and pin connections. figure 3-1b PT4701 calculation of resistor ad just values the adjust resistor value may also be calculated using an equation. note that the equation for r 1 [adjust up] is different to that for (r 2 ) [adjust down]. r 1 [adjust up] = v r r o C r s k ? 2 (v a C v o ) (r 2 ) [adjust down] = r o (2 v a C v r ) C r s k ? 2 (v o C v a ) where: v o = original output voltage (vo x ) v a = adjusted output voltage (va x ) v r = the reference voltage from table 3-2 r o = the resistance value in table 3-2 r s = the series resistance from table 3-2 (r 2 ) +vo x v x adj +vo x dc/dc module # # # # - see table 3-1 for pin connections, where vo x indicates vo 1 , or vo 2 ? vo x ? vo x to adjust the magnitude of a +v o & ? v o pair lower com figure 3-1a r 1 to adjust the magnitude of a +v o & ? v o pair higher # - see table 3-1 for pin connections, where vo x indicates vo 1 , or vo 2 +vo x v x adj +vo x dc/dc module # # # ? vo x ? vo x com adjust down: to decrease the magnitude of the compli- mentary output voltages, add a resistor (r 2 ) , between the appropriate vo x adj (vo 1 adj or vo 2 adj,) and the +vo x voltage rail. see figure 3-1(b) and table 3-1 for the resistor placement and pin connections. table 3-1; adjust resistor pin connections to adjust up to adjust down connect r 1 connect (r 2 ) from to from to vo x adj ? vo x vo x adj +vo x vo 1 17 16 17 14 vo 2 21 20 21 18 notes: 1. use only a single 1 % (or better) tolerance resistor in either the r 1 or (r 2 ) location to adjust a specific output. place the resistor as close to the isr as possible. 2. never connect capacitors to any of the vo x adj pins. any capacitance added to these control pins will affect the stability of the respective regulated output.
for technical support and more information, see inside back cover or visit www.ti.com application notes continued table 3-3 adjustment resistor values for vo 1 adj. resistor r 1 / (r 2 ) % adjust v a (req ? d) C10 % 7.20 v (86.4) k ? C 9 % 7.28 v (99.8) k ? C 8 % 7.36 v (117.0) k ? C 7 % 7.44 v (138.0) k ? C 6 % 7.52 v (167.0) k ? C 5 % 7.60 v (207.0) k ? C 4 % 7.68 v (267.0) k ? C 3 % 7.76 v (368.0) k ? C 2 % 7.84 v (569.0) k ? C 1 % 7.92 v (1.17) m ? 0 % 8.00 v + 1 % 8.08 v 203.0 k ? + 2 % 8.16 v 91.7 k ? + 3 % 8.24 v 54.5 k ? + 4 % 8.32 v 35.9 k ? + 5 % 8.40 v 24.7 k ? + 6 % 8.48 v 17.2 k ? + 7 % 8.56 v 11.9 k ? + 8 % 8.64 v 7.9 k ? + 9 % 8.72 v 4.8 k ? +10 % 8.80 v 2.3 k ? r 1 = black, r 2 = (blue) table 3-2 adjustment range and formula parameters vo 1 bus vo 2 bus v o (nom) 8.0 v 3.94 v v a (min) 7.2 v 3.55 v v a (max) 8.8 v 4.33 v v r 2.5 v 1.24 v r o (k ? ) 14.3 13.0 r s (k ? ? ? ? ? ) 20.0 16.2 PT4701 table 3-4 adjustment resistor values for vo 2 adj. resistor r 1 / (r 2 ) v a (req ? d) 3.546 v (80.3) k ? 3.585 v (92.5) k ? 3.625 v (108.0) k ? 3.664 v (127.0) k ? 3.704 v (153.0) k ? 3.743 v (190.0) k ? 3.782 v (245.0) k ? 3.822 v (336.0) k ? 3.861 v (519.0) k ? 3.900 v (1.07)m ? 3.940 v 3.979 v 188.0 k ? 4.019 v 86.1 k ? 4.058 v 52.0 k ? 4.098 v 34.9 k ? 4.137 v 24.7 k ? 4.176 v 17.9 k ? 4.216 v 13.0 k ? 4.255 v 9.4 k ? 4.295 v 6.5 k ? 4.334 v 4.3 k ? r 1 = black, r 2 = (blue)
application notes for technical support and more information, see inside back cover or visit www.ti.com PT4701 figure 3; PT4701 power-up sequence on/off output voltage sequencing the PT4701 converter power-up characteristics meet the requirements of texas instruments tnetd7112 dual-channel line-interface driver/receiver ics. all four outputs from the converter are internally sequenced to power up in unison. figure 3 shows the waveforms from a PT4701 following the application of power. there is a delay of appoximately 25 ms from the application power to the point that the output voltages begin to rise. the converter typically produces a fully regulated output within 75 ms.the waveforms of figure 3 were measured with loads of approximately 50% on each output, with an input source of 48 vdc. using the on/off enable controls on the PT4701 quad-output dc/dc converter the PT4701 is a quad-output dc/dc converter that is specifically designed for powering dsl line driver ics. the converter incorporates two output enable controls. en1 (pin 4) is the negative enable input, and en2 (pin 3) is the positive enable input. both inputs are electrically referenced to Cv in (pin 2) on the primary or input side of the converter. a pull-up resistor is not required, but may be added if desired. voltages of up to 70 v can be safely applied to the either of the enable pins. automatic (uvlo) power-up connecting en1 (pin 4) to -v in (pin 2) and leaving en2 (pin 3) open-circuit configures the converter for auto- matic power up. (see data sheet typical application). the converter control circuitry incorporates an under voltage lockout (uvlo) function, w hich disables the converter until the minimum specified input voltage is present at v in . (see data sheet specifications). the uvlo circuitry ensures a clean transition during power-up and power-down, allowing the converter to tolerate a slow- rising input voltage. for most applications en1 and en2, can be configured for automatic power-up. positive output enable (negative inhibit) to configure the converter for a positive enable func- tion, connect en1 (pin 4) to -v in (pin 2), and apply the system on/off control signal to en2 (pin 3). in this configuration, a low-level input voltage (-v in potential) applied to pin 3 disables the converter outputs. figure 1 is an example of this configuration. negative output enable (positive inhibit) to configure the converter for a negative enable function, en2 (pin 3) is left open circuit, and the system on/off control signal is applied to en1 (pin 4). a low-level input voltage (-v in potential) must then be applied to dc/dc module en 1* en 2 ? vin ? v in 1 =outputs off 3 4 2 bss138 dc/dc module en 1* en 2 ? vin ? v in 1 =outputs on 3 4 2 bss138 figure 2; negative enable configuration figure 1; positive enable configuration pin 4 in order to enable the outputs of the converter. an example of this configuration is detailed in figure 2. note: the converter will only produce and output voltage if a valid input voltage is applied to v in . +vo1 (2v/div) +vo2 (2v/div) ? vo2 (2v/div) ? vo1 (2v/div) horiz scale: 10ms/div

mechanical data mmsi071 ? october 2001 1 post office box 655303 ? dallas, texas 75265 enn (r?msip?t21) metal single?in-line module 4203487/a 10/01 2.58 (65,53) max. 1.46 (37,08) max 0.160 (4,06) typ. 0.040 (1,01) typ. 0.100 (2,54) typ. 0.025 (0,63) typ. 0.472 (12,00) max 1.62 (41,14) max pc layout 2.520 (64,00) 2.620 (66,54) 1.500 (38,10) note h 1.260 (32,00) 1.44 (36,57) 0.280 (7,11) 0.050 (1,27) 0.080 (2,03) 2 places 0.250 0.100 (2,54) 20 places 0.260 (6,60) ? 0.045 (1,14) min. 21 places 0.017 (0,43) typ. 0.080 (2,03) 0.160 (4,06) 0.110 (2,79) 0.040 (1,01) note e note e 4 places 0.032 (0,81) typ. 0.140 (3,55) min. see note f ? 0.065 (1,65) min. 4 places plated through holes. see note g. plated through, note j note g suffix a 1 1 (6,35) 0.51 (12,95) notes: a. all linear dimensions are in inches (mm). b. this drawing is subject to change without notice. c. 2 place decimals are 0.030 ( 0,76mm). d. 3 place decimals are 0.010 ( 0,25mm). e. recommended mechanical keep out area. f. electrical pin length mounted on printed circuit board, from seating plane to pin end. g. the case is electrically uncommitted. the recommended connection is to secondary ground. h. no copper, power or signal traces in this area. j. some pins may not be present, see product specifications.
mechanical data mmsi072 ? october 2001 1 post office box 655303 ? dallas, texas 75265 enp (r?msip?g21) metal single?in-line module 4203488/a 10/01 2.58 (65,53) max. 1.46 (37,08) max 0.160 (4,06) typ. 0.040 (1,01) typ. 0.100 (2,54) typ. 0.025 (0,63) typ. 0.472 (12,00) max 1.62 (41,14) max pc layout 2.520 (64,00) 2.620 (66,54) 1.500 (38,10) note j 1.260 (32,00) 1.44 (36,57) 0.280 (7,11) 0.050 (1,27) 0.080 (2,03) 2 places 0.250 0.100 (2,54) 20 places 0.260 (6,60) 0.040 (1,01) note e 0.032 (0,81) typ. ? 0.065 (1,65) min. 4 places suffix c 1 1 (6,35) 0.51 (12,95) detail ?a? note g, h note f 0.070 (1,77) 0.090 (2,28) see note h. plated through holes. 0.140 (3,55) gage plane 0 ? 60 0.080 (2,03) seating plane 0.004 (0,10) 0.017 (0,43) typ. note i 0.230 (5,84) 0.210 (5,33) 0.050 (1,27) 0.165 (4,19) 0.050 (1,27) 21 places 0.100 (2,54) 0.050 (1,27) 0.100 (2,54) note k note e 2 places detail ?a? notes: a. all linear dimensions are in inches (mm). b. this drawing is subject to change without notice. c. 2 place decimals are 0.030 ( 0,76mm). d. 3 place decimals are 0.010 ( 0,25mm). e. recommended mechanical keep out area. f. vias are recommended to improve copper adhesion. g. solder mask openings to copper island for solder joints to mechanical pins. h. the case is electrically uncommitted. the recommended connection is to secondary ground. i. power pin connections should utilize two or more vias per input, ground and output pin. j. no copper, power or signal traces in this area. k. some pins may not be present, see product specifications.
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